ECGR2181 - Logic Systems Design I

UNC- Charlotte ECGR2181-001- Spring 2005

Logic Systems Design I

Lecture, 4:00 - 5:20 PM, T-TH, Smith 218


Homework	This page updated May 4, 2005

Homework Template • Homework 1 • Homework 2 • Homework 3 • Homework 4 • Homework 5 • Homework 6 • Computer Lab 1 • Homework 7 • Homework 8 • Computer Lab 2 • Homework 9 • Homework 10 • Homework 11 • Computer Lab 3

Computer Lab Assignment 3, Due Tuesday, May 3, BEGINNING OF CLASS!!!!

While in our lab, go through the Lab 3 Assignment Instructions.
Use this lab report template for the report which is due. Don't forget to print your VHDL code files and attach them to the report.

Homework 11, Due Tuesday, May 3, BEGINNING OF CLASS!!!!

Homework 10, Due Tuesday, April 26, BEGINNING OF CLASS!!!!

Problems 5.57a,b; 5.85 Show all work! Also, question 0 is: "How long did this homework take you?"

Homework 9, Due Tuesday, April 19, BEGINNING OF CLASS!!!!

Problems 5.28, 5.77. Show all work! Also, question 0 is: "How long did this homework take you?"

Computer Lab Assignment 2, Due Tuesday, April 12, BEGINNING OF CLASS!!!!

While in our lab, go through the Lab 2 Assignment Instructions.
Use this lab report template for the report which is due. Don't forget to print your VHDL code files and attach them to the report.

Homework 8, Due Tuesday, April 4, BEGINNING OF CLASS!!!!

Problems 5.19d, 5.20. Show all work! Also, question 0 is: "How long did this homework take you?" Do them before the test - they may appear on the test!

Homework 7, Due Thursday, March 24, BEGINNING OF CLASS!!!!

Due: Draw a flow chart which shows the processes of creating a design all the way through programming and testing the FPGA board. Show blocks representing large activities you need to do (not individual keystrokes!). Limit your flowchart to 20 blocks.

Computer Lab Assignment 1, Due Tuesday, March 22, BEGINNING OF CLASS!!!!

While in our lab, go through the Lab 1 Assignment Instructions and the Download exercises.
Fill out and turn in this exercise sheet. make sure a TA or instructor has viewed your simulation and programmed FPGA board.

Homework 6, Due Thursday, March 3, BEGINNING OF CLASS!!!!

Divide 0x4A2 by 0xE; do Problems 4.13d; 4.19d; write a Verilog Module for F=SA,B,C(0,1,5,7). Show all work! Also, question 0 is: "How long did this homework take you?"

Homework 5, Due Thursday, February 17, BEGINNING OF CLASS!!!!

Problems 4.6b, 4.7c, 4.8a, 4.9c. Show all work! Also, question 0 is: "How long did this homework take you?" Do them before the test - they may appear on the test!

Homework 4, Due Tuesday, February 8, BEGINNING OF CLASS!!!!

Do problems 3.1, 3.5, 3.11, 4.1 from the book. Show all work! Also, question 0 is: "How long did this homework take you?"
.

Homework 3, Due Tuesday, February 1, BEGINNING OF CLASS!!!!

Assignment (pdf file).
Homework 3 hint: Each ASCII character needs 7 bits. Each character has its own start, stop, and parity bit.

Homework 2, Due Tuesday, January 25, BEGINNING OF CLASS!!!!

Do problems 2.5a,b,c,f,h; 2.7a, 2.8a, 2.15, 2.17 from the book. Show all work! Also, question 0 is: "How long did this homework take you?"

Homework 1, Due Tuesday, January 18, BEGINNING OF CLASS!!!!