Instruction Set

Introduction:

The following is a list of the most used 68000 instructions. Each will have a description of the instruction's operation, the instruction's syntax, and a table specifying which modes are available for both the source and destination effective address fields.

Legend:

The example table below will appear with each instruction that contains the Effective Address (<ea>) symbol in the syntax of the instruction. This table specifies which addressing modes may be used in the effective address field for that particular instruction.

Addressing Mode
S/D
Addressing Mode
S/D
Dn
.
d(An,Xn)
.
An
.
Abs. Sh
.
(An)
.
Abs. Long
.
(An)+
.
Imm.
.
-(An)
.
d(PC)
.
d(An)
.
d(PC,Xn)
.
DnData Register Direct
AnAddress Register Direct
(An)Address Register Indirect
(An)+Address Register Indirect with postincrement
-(An)Address Register Indirect with predecrement
d(An)Address Register Indirect with displacement
d(An,Xn)Address Register Indirect with displacement and index
Abs. ShAbsolute Short
Abs. LongAbsolute Long
Imm.Immediate
d(PC)Program Counter Relative with displacement
d(PC,Xn)Program Counter Relative with displacement and index
SAn "S" in the S/D column indicates this mode is available for the
source effective address field
DAn "D" in the S/D column indicates this mode is available for the
destination effective address field

The Instruction Set:

ABCD:Add decimal (Binary Coded Decimal - BCD) with extend
Operation:Source + Destination + X => Destination
Syntax:ABCD Dy,Dx or
ABCD -(Ay),-(Ax)
Attributes:Size = Byte only
This is a byte only instruction. The source packed BCD number is added to the destination packed BCD number (with the extend bit) and the result is stored in the destination effective address. The operands must be stored in the lower byte of 2 data registers or in memory. If the operands are stored in memory, they must be referenced in ARI with Predecrement Mode.

ADD:Add binary
Operation:Source + Destination => Destination
Syntax:ADD <ea>,Dn or
ADD Dn,<ea>
Attributes:Size = Byte, Word, Longword
Adds the source operand to the destination operand in binary and stores the result in the destination effective address.
Addressing Mode
S/D
Addressing Mode
S/D
Dn
S
d(An,Xn)
SD
An
S
Abs. Sh
SD
(An)
SD
Abs. Long
SD
(An)+
SD
Imm.
S
-(An)
SD
d(PC)
S
d(An)
SD
d(PC,Xn)
S
ADDA:Add Address
Operation:Source + Destination => Destination
Syntax:ADDA <ea>,An
Attributes:Size = Word, Longword
Adds the source operand to the value in an Address Register in binary and stores the result in the address register. The destination operand must be an Address Register.
Addressing Mode
S/D
Addressing Mode
S/D
Dn
S
d(An,Xn)
S
An
S
Abs. Sh
S
(An)
S
Abs. Long
S
(An)+
S
Imm.
S
-(An)
S
d(PC)
S
d(An)
S
d(PC,Xn)
S
ADDI:Add Immediate Data
Operation:Immediate Data + Destination => Destination
Syntax:ADDI #data,<ea>
Attributes:Size = Byte, Word, Longword
Adds immediate data to the value in the effective address and stores the result in the effective address.
Addressing Mode
S/D
Addressing Mode
S/D
Dn
D
d(An,Xn)
D
An
.
Abs. Sh
D
(An)
D
Abs. Long
D
(An)+
D
Imm.
.
-(An)
D
d(PC)
.
d(An)
D
d(PC,Xn)
.
ADDQ:Add Quick Immediate Data
Operation:Immediate Data + Destination => Destination
Syntax:ADDQ #data,<ea>
Attributes:Size = Byte, Word, Longword
Adds an immediate value of 1 to 8 to the value in the effective address and stores the result in the effective address. If the destination effective address is an address register, word or longword must be specified, the CCR is unaffected, and the complete address register is used regardless of the size specified.
Addressing Mode
S/D
Addressing Mode
S/D
Dn
D
d(An,Xn)
D
An
D
Abs. Sh
D
(An)
D
Abs. Long
D
(An)+
D
Imm.
.
-(An)
D
d(PC)
.
d(An)
D
d(PC,Xn)
.
ADDX:Add binary with extend
Operation:Source + Destination + X => Destination
Syntax:ADDX Dy,Dx or
ADDX -(Ay),-(Ax)
Attributes:Size = Byte, Word, Longword
The source operand is added to the destination operand (with the extend bit) and the result is stored in the destination effective address. The operands must be stored in the data registers or in memory. If the operands are stored in memory, they must be referenced in ARI with Predecrement Mode.
AND:Logical AND
Operation:Source Ù Destination => Destination
Syntax:AND <ea>,Dn or
AND Dn,<ea>
Attributes:Size = Byte, Word, Longword
Performs a Logical AND operation on the source and destination operand and stores the result in the destination effective address.
Addressing Mode
S/D
Addressing Mode
S/D
Dn
S
d(An,Xn)
SD
An
.
Abs. Sh
SD
(An)
SD
Abs. Long
SD
(An)+
SD
Imm.
S
-(An)
SD
d(PC)
S
d(An)
SD
d(PC,Xn)
S

ANDI:Logical AND Immediate
Operation:Immediate Data Ù Destination => Destination
Syntax:ANDI #data ,Dn
Attributes:Size = Byte, Word, Longword
Performs a Logical AND operation on the immediate data and the destination operand and stores the result in the destination effective address.
Addressing Mode
S/D
Addressing Mode
S/D
Dn
D
d(An,Xn)
D
An
.
Abs. Sh
D
(An)
D
Abs. Long
D
(An)+
D
Imm.
.
-(An)
D
d(PC)
.
d(An)
D
d(PC,Xn)
.

ANDI to CCR:Logical AND Immediate to Condition Code Register
Operation:Immediate Data Ù CCR => CCR
Syntax:ANDI #data,CCR
Attributes:Size = Byte
Performs a Logical AND operation on the immediate data and the Condition Code Register bits and stores the result in the Condition Code Register.

ASL,ASR:Arithmetic Shift
Operation:Destination Shifted by (Count) => Destination
Syntax:ASd Dx,Dy or
ASd #data,Dy
ASd <ea>
d = L or R
Attributes:Size = Byte, Word, Longword
Register Dy is shifted by the amount specified by the count. The count is held in Immediate data (range = 1 to 8) or in a data register (Dx; the count is greater than 8). Memory locations specified by <ea> can only be shifted once and are restricted to word size data.
ASL
ASR
Addressing Mode
S/D
Addressing Mode
S/D
Dn
.
d(An,Xn)
D
An
.
Abs. Sh
D
(An)
D
Abs. Long
D
(An)+
D
Imm.
.
-(An)
D
d(PC)
.
d(An)
D
d(PC,Xn)
.

Bcc:Conditional Branch
Operation:If (condition true) then PC + d => PC
Syntax:Bcc label
Attributes:Size = Byte, Word
If the condition specified by "cc" is true, the displacement "d" is added to the Program Counter (PC) so that program execution continues at the instruction found at "label".
Conditions:Replace "cc" above with one of the following conditions:
(The follow are bits in the condition code register -CZNVX)
(+ = OR, & = AND, / = NOT)
CC Carry ClearC=0 LELess or EqualZ+(N&/V)+(/N&V)=1
CSCarry SetC=1 LSLower or SameC + Z = 1
EQEqualZ=1 LTLess Than(N & /V)+(/N & V)=1
NENot EqualZ=0 GE Greater or Equal (N&V)+(/N&/V)=1
PLPlusN=0 GTGreater Than(N&V&Z)+(/N&/V&Z)=1
MIMinusN=1 HIHigher/C&/Z=1
VCOverflow ClearV=0 VSOverflow SetV=1

BRA:Unconditional Branch (Branch Always)
Operation:PC + d => PC
Syntax:BRA label
Attributes:Size = Byte, Word
The displacement "d" is added to the Program Counter (PC) so that program execution continues at the instruction found at "label".

BSR:Branch to Subroutine
Operation:SP-4 =>SP, PC => (SP), PC + d => PC
Syntax:BSR label
Attributes:Size = Byte, Word
Pushes the longword address in the PC onto the stack (address of the instruction immediately following the BSR instruction), and then transfers execution to the address at "label".

BCHG:Test a bit and change
Operation:see below
Syntax:BCHG Dn,<ea> or
BCHG #data,<ea>
Attributes:Size = Byte, Longword
This instruction tests a bit (specified by #data or the value in a Data Register - Dn) and sets or resets the Z bit accordingly (if the tested bit is 0, the Z bit gets set), then changes the state of the tested bit.
Addressing Mode
S/D
Addressing Mode
S/D
Dn
D
d(An,Xn)
D
An
.
Abs. Sh
D
(An)
D
Abs. Long
D
(An)+
D
Imm.
.
-(An)
D
d(PC)
.
d(An)
D
d(PC,Xn)
.

BCLR:Test a bit and clear
Operation:see below
Syntax:BCHG Dn,<ea> or
BCHG #data,<ea>
Attributes:Size = Byte, Longword
This instruction tests a bit (specified by #data or the value in a Data Register - Dn) and sets or resets the Z bit accordingly (if the tested bit is 0, the Z bit gets set), then clears the tested bit.
Addressing Mode
S/D
Addressing Mode
S/D
Dn
D
d(An,Xn)
D
An
.
Abs. Sh
D
(An)
D
Abs. Long
D
(An)+
D
Imm.
.
-(An)
D
d(PC)
.
d(An)
D
d(PC,Xn)
.

BSET:Test a bit and set
Operation:see below
Syntax:BCHG Dn,<ea> or
BCHG #data,<ea>
Attributes:Size = Byte, Longword
This instruction tests a bit (specified by #data or the value in a Data Register - Dn) and sets or resets the Z bit accordingly (if the tested bit is 0, the Z bit gets set), then sets the tested bit.
Addressing Mode
S/D
Addressing Mode
S/D
Dn
D
d(An,Xn)
D
An
.
Abs. Sh
D
(An)
D
Abs. Long
D
(An)+
D
Imm.
.
-(An)
D
d(PC)
.
d(An)
D
d(PC,Xn)
.

BTST:Test a bit
Operation:see below
Syntax:BCHG Dn,<ea> or
BCHG #data,<ea>
Attributes:Size = Byte, Longword
This instruction tests a bit (specified by #data or the value in a Data Register - Dn) and sets or resets the Z bit accordingly (if the tested bit is 0, the Z bit gets set).
Addressing Mode
S/D
Addressing Mode
S/D
Dn
D
d(An,Xn)
D
An
.
Abs. Sh
D
(An)
D
Abs. Long
D
(An)+
D
Imm.
.
-(An)
D
d(PC)
.
d(An)
D
d(PC,Xn)
.

CLR:Clear an Operand
Operation:0 => Destination
Syntax:CLR <ea>
Attributes:Size = Byte, Word, Longword
Clears the destination operand
Addressing Mode
S/D
Addressing Mode
S/D
Dn
D
d(An,Xn)
D
An
.
Abs. Sh
D
(An)
D
Abs. Long
D
(An)+
D
Imm.
.
-(An)
D
d(PC)
.
d(An)
D
d(PC,Xn)
.

CMP:Compare
Operation:Destination - Source => CCR
Syntax:CMP <ea>,Dn
Attributes:Size = Byte, Word, Longword
Subtracts the Source operand from the destination operand and sets the appropriate bits in the CCR. The destination register must be a Data Register.
Addressing Mode
S/D
Addressing Mode
S/D
Dn
S
d(An,Xn)
S
An
S
Abs. Sh
S
(An)
S
Abs. Long
S
(An)+
S
Imm.
S
-(An)
S
d(PC)
S
d(An)
S
d(PC,Xn)
S

CMPA:Compare Address Register
Operation:Destination - Source => CCR
Syntax:CMP <ea>,An
Attributes:Size = Word, Longword
Subtracts the Source operand from the destination operand and sets the appropriate bits in the CCR. The destination register must be an Address Register.
Addressing Mode
S/D
Addressing Mode
S/D
Dn
S
d(An,Xn)
S
An
S
Abs. Sh
S
(An)
S
Abs. Long
S
(An)+
S
Imm.
S
-(An)
S
d(PC)
S
d(An)
S
d(PC,Xn)
S

CMPI:Compare Immediate Data
Operation:Destination - Immediate Data => CCR
Syntax:CMP #data,<ea>
Attributes:Size = Byte, Word, Longword
Subtracts the immediate data from the destination operand and sets the appropriate bits in the CCR.
Addressing Mode
S/D
Addressing Mode
S/D
Dn
D
d(An,Xn)
D
An
.
Abs. Sh
D
(An)
D
Abs. Long
D
(An)+
D
Imm.
.
-(An)
D
d(PC)
D
d(An)
D
d(PC,Xn)
D

CMPM:Compare Memory
Operation:Destination - Source => CCR
Syntax:CMP (Ax)+,(Ay)+
Attributes:Size = Byte, Word, Longword
Subtracts the source operand from the destination operand and sets the appropriate bits in the CCR.

DBcc:Test, Decrement & Branch
Operation:If (condition false) then (Dn-1=>Dn; If Dn ¹ -1the PC+d=> PC)
Syntax:DBcc Dn,label
Attributes:Size = Word
This instruction is used to control conditional loops. If the condition specified by "cc" is false, the data register is decremented and tested against -1. If the value in the data register = -1 the displacement "d" is added to the Program Counter (PC) so that program execution continues at the instruction found at "label". If the condition is true the displacement "d" is added to the Program Counter (PC) so that program execution continues at the instruction found at "label". This instruction only works on the lower word of the data register specified.
Conditions:Replace "cc" above with one of the following conditions:
(The follow are bits in the condition code register -CZNVX)
(+ = OR, & = AND, / = NOT)
CC Carry ClearC=0 LELess or EqualZ+(N&/V)+(/N&V)=1
CSCarry SetC=1 LSLower or SameC + Z = 1
EQEqualZ=1 LTLess Than(N & /V)+(/N & V)=1
NENot EqualZ=0 GE Greater or Equal (N&V)+(/N&/V)=1
PLPlusN=0 GTGreater Than(N&V&Z)+(/N&/V&Z)=1
MIMinusN=1 HIHigher/C&/Z=1
VCOverflow ClearV=0 VSOverflow SetV=1

DIVS:Divide Signed
Operation:Destination/Source => Destination
Syntax:DIVS.W <ea>,Dn
Attributes:Size = Word
Divides a 32 bit destination operand by a 16 bit signed source operand and places the result in the destination effective address. The upper 16 bits of the results are the remainder followed by the quotient in the lower 16 bits.
Addressing Mode
S/D
Addressing Mode
S/D
Dn
S
d(An,Xn)
S
An
.
Abs. Sh
S
(An)
S
Abs. Long
S
(An)+
S
Imm.
S
-(An)
S
d(PC)
S
d(An)
S
d(PC,Xn)
S

DIVU:Divide Unsigned
Operation:Destination/Source => Destination
Syntax:DIVS.W <ea>,Dn
Attributes:Size = Word
Divides a 32 bit destination operand by a 16 bit unsigned source operand and places the result in the destination effective address. The upper 16 bits of the results are the remainder followed by the quotient in the lower 16 bits.
Addressing Mode
S/D
Addressing Mode
S/D
Dn
S
d(An,Xn)
S
An
.
Abs. Sh
S
(An)
S
Abs. Long
S
(An)+
S
Imm.
S
-(An)
S
d(PC)
S
d(An)
S
d(PC,Xn)
S

EOR:Exclusive OR
Operation:Destination EOR Source => Destination
Syntax:EOR Dn,<ea>
Attributes:Size =Byte, Word, Longword
Performs an Exclusive OR between the destination operand and the source operand and stores the result in the destination effective address.
Addressing Mode
S/D
Addressing Mode
S/D
Dn
D
d(An,Xn)
D
An
.
Abs. Sh
D
(An)
D
Abs. Long
D
(An)+
D
Imm.
.
-(An)
D
d(PC)
.
d(An)
D
d(PC,Xn)
.

EORI:Exclusive OR Immediate
Operation:Immediate Data EOR Destination => Destination
Syntax:EORI #data,<ea>
Attributes:Size =Byte, Word, Longword
Performs an Exclusive OR between the destination operand and the immediate data and stores the result in the destination effective address.
Addressing Mode
S/D
Addressing Mode
S/D
Dn
D
d(An,Xn)
D
An
.
Abs. Sh
D
(An)
D
Abs. Long
D
(An)+
D
Imm.
.
-(An)
D
d(PC)
.
d(An)
D
d(PC,Xn)
.

EORI to CCR:Exclusive OR Immediate to CCR
Operation:Immediate Data EOR CCR => CCR
Syntax:EORI #data,CCR
Attributes:Size =Byte
Performs an Exclusive OR between the Condition Code Register bits and the immediate data and stores the result in the Condition Code Register.

EXG:Exchange Regsiters
Operation:Rx <=> Ry
Syntax:EXG Dx,Dy
EXG Ax,Ay
EXG Dx,Ay
EXG Ax,Dy
Attributes:Size =Longword
Exchanges the contents of source and destination effective addresses.

EXT:Sign Extend Register
Operation:Sign Extend Destination => Destination
Syntax:EXT.W Dn byte to word
EXT.L Dn word to longword
Attributes:Size =Word, Longword
Sign extends a byte to a word or a word to a longword

JMP:Jump
Operation:Destination Address => PC
Syntax:JMP <ea>
Attributes:Size = unsized
Program execution continues at the address specified by the instruction. The effective address could be a label which would be converted to an absolute address.

Addressing Mode
S/D
Addressing Mode
S/D
Dn
.
d(An,Xn)
D
An
.
Abs. Sh
D
(An)
D
Abs. Long
D
(An)+
.
Imm.
.
-(An)
.
d(PC)
D
d(An)
D
d(PC,Xn)
D

JSR:Jump to Subroutine
Operation:SP-4=>SP; PC=>(SP); Destination Address => PC
Syntax:JSR <ea>
Attributes:Size = unsized
The current Program Counter (the address of the instruction immediately following the JSR instruction) is pushed onto the stack, then the address specified by the effective address is stored in the PC. Program execution continues at that address. The effective address could be a label which would be converted to an absolute address.
Addressing Mode
S/D
Addressing Mode
S/D
Dn
.
d(An,Xn)
D
An
.
Abs. Sh
D
(An)
D
Abs. Long
D
(An)+
.
Imm.
.
-(An)
.
d(PC)
D
d(An)
D
d(PC,Xn)
D

LSL,LSR:Logic Shift
Operation:Destination Shifted by (Count) => Destination
Syntax:LSd Dx,Dy or
LSd #data,Dy
LSd <ea>
d = L or R
Attributes:Size = Byte, Word, Longword
Register Dy is shifted by the amount specified by the count. The count is held in Immediate data (range = 1 to 8) or in a data register (Dx; the count is greater than 8). Memory locations specified by <ea> can only be shifted once and are restricted to word size data.
LSL
LSR
Addressing Mode
S/D
Addressing Mode
S/D
Dn
.
d(An,Xn)
D
An
.
Abs. Sh
D
(An)
D
Abs. Long
D
(An)+
D
Imm.
.
-(An)
D
d(PC)
.
d(An)
D
d(PC,Xn)
.

MOVE:Move Data from Source to Destination
Operation:Source => Destination
Syntax:MOVE <ea>,<ea>
Attributes:Size = Byte, Word, Longword
Moves the data from the source effective address to the destination effective address and sets the CCR appropriately with respect to the data.
Addressing Mode
S/D
Addressing Mode
S/D
Dn
SD
d(An,Xn)
SD
An
S
Abs. Sh
SD
(An)
SD
Abs. Long
SD
(An)+
SD
Imm.
S
-(An)
SD
d(PC)
S
d(An)
SD
d(PC,Xn)
S

MOVEA:Move Data from Source to Address Register
Operation:Source => Address Register
Syntax:MOVE <ea>,An
Attributes:Size = Word, Longword
Moves the data from the source effective address to the address register specified.
Addressing Mode
S/D
Addressing Mode
S/D
Dn
S
d(An,Xn)
S
An
S
Abs. Sh
S
(An)
S
Abs. Long
S
(An)+
S
Imm.
S
-(An)
S
d(PC)
S
d(An)
S
d(PC,Xn)
S

MOVE from CCR:Move Data from the CCR
Operation:CCR => Destination
Syntax:MOVE CCR,<ea>
Attributes:Size = Word
Moves the data from the condition code register to the destination effective address.
Addressing Mode
S/D
Addressing Mode
S/D
Dn
D
d(An,Xn)
D
An
.
Abs. Sh
D
(An)
D
Abs. Long
D
(An)+
D
Imm.
.
-(An)
D
d(PC)
.
d(An)
D
d(PC,Xn)
.

MOVE to CCR:Move Data to the CCR
Operation:Source => CCR
Syntax:MOVE <ea>,CCR
Attributes:Size = Word
Moves the data to the condition code register from the source effective address.
Addressing Mode
S/D
Addressing Mode
S/D
Dn
S
d(An,Xn)
S
An
.
Abs. Sh
S
(An)
S
Abs. Long
S
(An)+
S
Imm.
S
-(An)
S
d(PC)
S
d(An)
S
d(PC,Xn)
S

MOVM:Move Multiple Registers
Operation:Register List => Destination or Source => Register List
Syntax:MOVEM register list,<ea> or
MOVEM <ea>,register list
Attributes:Size = Word, Longword
Moves the contents of the selected registers to/from consecutive memory locations specified by the effective address field. The order of registers is always D0-D7 then A0-A7. For example: the instruction is MOVEM.W D7/D4/A6/D0-D2/A1,$4000. In this example the lower word of D0 is moved to $4000 & $4001, D1 to $4002 & $4003, D2 to $4004 & $4005, D4 to $4006 & $4007, D7 to $4008 & $4009, A1 to $400A & $400B, and A6 to $400C & $400D.
Addressing Mode
S/D
Addressing Mode
S/D
Dn
.
d(An,Xn)
SD
An
.
Abs. Sh
SD
(An)
SD
Abs. Long
SD
(An)+
S
Imm.
.
-(An)
D
d(PC)
S
d(An)
SD
d(PC,Xn)
S

MOVP:Move to/from Peripherals
Operation:Source => Destination
Syntax:MOVEP Dn,d(An) or
MOVEP d(An),Dn
Attributes:Size = Word, Longword
Moves data between a data register and alternate bytes within memory (usually reserved for a peripheral device). Because 68XX peripherals will respond to alternate addresses, this instruction is meant to move multiple bytes of data between the 68XX peripheral device and a data register.

MOVQ:Move Quick
Operation:Immediate data => Destination
Syntax:MOVE #data,Dn
Attributes:Size = Longword
Moves a byte of data to a data register and sign extends the byte to a longword. The data is included in the 16 bit op code for the instruction.

MULS:Signed Multiply
Operation:Source * Destination => Destination
Syntax:MULS <ea>,Dn 16x16=>32
Attributes:Size = Word
Multiplies two signed 16 bit numbers yielding a signed 32 bit result.
Addressing Mode
S/D
Addressing Mode
S/D
Dn
S
d(An,Xn)
S
An
.
Abs. Sh
S
(An)
S
Abs. Long
S
(An)+
S
Imm.
S
-(An)
S
d(PC)
S
d(An)
S
d(PC,Xn)
S

MULU:Unsigned Multiply
Operation:Source * Destination => Destination
Syntax:MULS <ea>,Dn 16x16=>32
Attributes:Size = Word
Multiplies two unsigned 16 bit numbers yielding an unsigned 32 bit result.
Addressing Mode
S/D
Addressing Mode
S/D
Dn
S
d(An,Xn)
S
An
.
Abs. Sh
S
(An)
S
Abs. Long
S
(An)+
S
Imm.
S
-(An)
S
d(PC)
S
d(An)
S
d(PC,Xn)
S

NBCD:Negate BCD with Extend
Operation:0 - Destination - X => Destination
Syntax:NBCD <ea>
Attributes:Size = Byte
Subtracts the destination operand (a BCD number) and the extend bit from 0.
Addressing Mode
S/D
Addressing Mode
S/D
Dn
D
d(An,Xn)
D
An
.
Abs. Sh
D
(An)
D
Abs. Long
D
(An)+
D
Imm.
.
-(An)
D
d(PC)
.
d(An)
D
d(PC,Xn)
.

NEG:Negate
Operation:0 - Destination => Destination
Syntax:NBCD <ea>
Attributes:Size = Byte, Word, Longword
Subtracts the destination operand from 0.
Addressing Mode
S/D
Addressing Mode
S/D
Dn
D
d(An,Xn)
D
An
.
Abs. Sh
D
(An)
D
Abs. Long
D
(An)+
D
Imm.
.
-(An)
D
d(PC)
.
d(An)
D
d(PC,Xn)
.

NEGX:Negate with extend
Operation:0 - Destination - X => Destination
Syntax:NBCD <ea>
Attributes:Size = Byte, Word, Longword
Subtracts the destination operand and the extend bit from 0.
Addressing Mode
S/D
Addressing Mode
S/D
Dn
D
d(An,Xn)
D
An
.
Abs. Sh
D
(An)
D
Abs. Long
D
(An)+
D
Imm.
.
-(An)
D
d(PC)
.
d(An)
D
d(PC,Xn)
.

NOP:No Operation
Operation:none
Syntax:NOP
Attributes:unsized
Increment PC to address of next instruction, otherwise performs no operation, but does take up some processor time. Used to fine tune timing loops.

NOT:Logical Compliment
Operation:/ Destination => Destination
Syntax:NOT <ea>
Attributes:Size = Byte, Word, Longword
Compliments the destination operand.
Addressing Mode
S/D
Addressing Mode
S/D
Dn
D
d(An,Xn)
D
An
.
Abs. Sh
D
(An)
D
Abs. Long
D
(An)+
D
Imm.
.
-(An)
D
d(PC)
.
d(An)
D
d(PC,Xn)
.

OR:Inclusive OR
Operation:Source OR Destination => Destination
Syntax:OR <ea>,Dn or
OR Dn,<ea>
Attributes:Size = Byte, Word, Longword
Logically ORs the source and destination operands and stores the results in the destination effective address.
Addressing Mode
S/D
Addressing Mode
S/D
Dn
S
d(An,Xn)
SD
An
.
Abs. Sh
SD
(An)
SD
Abs. Long
SD
(An)+
S
Imm.
S
-(An)
SD
d(PC)
S
d(An)
SD
d(PC,Xn)
S

ORI:Immediate Inclusive OR
Operation:Immediate Data OR Destination => Destination
Syntax:ORI #data,<ea>
Attributes:Size = Byte, Word, Longword
Logically ORs the immdiate data and destination operand and stores the results in the destination effective address.
Addressing Mode
S/D
Addressing Mode
S/D
Dn
D
d(An,Xn)
D
An
.
Abs. Sh
D
(An)
D
Abs. Long
D
(An)+
D
Imm.
.
-(An)
D
d(PC)
.
d(An)
D
d(PC,Xn)
.

ORI to CCR:Inclusive OR with CCR
Operation:Immediate Data OR CCR => CCR
Syntax:ORI #data,CCR
Attributes:Size = Byte
Logically ORs the immdiate data and the condition code register and stores the results in the condition code register.

ROR,ROL:Rotate
Operation:Destination Rotated by (Count) => Destination
Syntax:ROd Dx,Dy or
ROd #data,Dy
ROd <ea>
d = L or R
Attributes:Size = Byte, Word, Longword
Register Dy is rotated by the amount specified by the count. The count is held in Immediate data (range = 1 to 8) or in a data register (Dx; the count is greater than 8). Memory locations specified by <ea> can only be rotated once and are restricted to word size data.
ROL
ROR
Addressing Mode
S/D
Addressing Mode
S/D
Dn
.
d(An,Xn)
D
An
.
Abs. Sh
D
(An)
D
Abs. Long
D
(An)+
D
Imm.
.
-(An)
D
d(PC)
.
d(An)
D
d(PC,Xn)
.

ROXR,ROXL:Rotate with extend
Operation:Destination Rotated by (Count) => Destination
Syntax:ROXd Dx,Dy or
ROXd #data,Dy
ROXd <ea>
d = L or R
Attributes:Size = Byte, Word, Longword
Register Dy is rotated by the amount specified by the count. The count is held in Immediate data (range = 1 to 8) or in a data register (Dx; the count is greater than 8). Memory locations specified by <ea> can only be rotated once and are restricted to word size data.
ROXL
ROXR
Addressing Mode
S/D
Addressing Mode
S/D
Dn
.
d(An,Xn)
D
An
.
Abs. Sh
D
(An)
D
Abs. Long
D
(An)+
D
Imm.
.
-(An)
D
d(PC)
.
d(An)
D
d(PC,Xn)
.

RTS:Return from Subroutine
Operation:(SP)=>PC
Syntax:RTS
Attributes:Size = unsized
Pulls the PC off the stack and continues program execution at the new PC.

SBCD:Subtract decimal (Binary Coded Decimal - BCD) with extend
Operation:Source - Destination - X => Destination
Syntax:SBCD Dy,Dx or
SBCD -(Ay),-(Ax)
Attributes:Size = Byte only
This is a byte only instruction. The source packed BCD number is subtracted from the destination packed BCD number (with the extend bit) and the result is stored in the destination effective address. The operands must be stored in the lower byte of 2 data registers or in memory. If the operands are stored in memory, they must be referenced in ARI with Predecrement Mode.

SUB:Subtract
Operation:Destination - Source => Destination
Syntax:SUB <ea>,Dn or
SUB Dn,<ea>
Attributes:Size = Byte, Word, Longword
Subtracts the source operand from the destination operand and stores the result in the destination location.
Addressing Mode
S/D
Addressing Mode
S/D
Dn
S
d(An,Xn)
SD
An
S
Abs. Sh
SD
(An)
SD
Abs. Long
SD
(An)+
SD
Imm.
S
-(An)
SD
d(PC)
S
d(An)
SD
d(PC,Xn)
S

SUBA:Subtract Address
Operation:Destination - Source => Destination
Syntax:SUBA <ea>,An
Attributes:Size = Word, Longword
Subtracts the source operand from an address register and stores the result in the address register.
Addressing Mode
S/D
Addressing Mode
S/D
Dn
S
d(An,Xn)
S
An
S
Abs. Sh
S
(An)
S
Abs. Long
S
(An)+
S
Imm.
S
-(An)
S
d(PC)
S
d(An)
S
d(PC,Xn)
S

SUBI:Subtract Immediate data
Operation:Destination - Immediate data => Destination
Syntax:SUBI #data,<ea>
Attributes:Size = Byte, Word, Longword
Subtracts the immediate data from destination operand and stores the result in the destination location.
Addressing Mode
S/D
Addressing Mode
S/D
Dn
D
d(An,Xn)
D
An
.
Abs. Sh
D
(An)
D
Abs. Long
D
(An)+
D
Imm.
.
-(An)
D
d(PC)
.
d(An)
D
d(PC,Xn)
.

SUBQ:Subtract Immediate data
Operation:Destination - Immediate data => Destination
Syntax:SUBQ #data,<ea>
Attributes:Size = Byte, Word, Longword
Subtracts the immediate data (1 to 8) from the destination operand and stores the result in the destination location. Only word and longword are allowed with Address Registers.
Addressing Mode
S/D
Addressing Mode
S/D
Dn
D
d(An,Xn)
D
An
D
Abs. Sh
D
(An)
D
Abs. Long
D
(An)+
D
Imm.
.
-(An)
D
d(PC)
.
d(An)
D
d(PC,Xn)
.

SUBX:Subtract binary with extend
Operation:Source - Destination - X => Destination
Syntax:SUBX Dy,Dx or
SUBX -(Ay),-(Ax)
Attributes:Size = Byte, Word, Longword
The source operand is subtracted from the destination operand (with the extend bit) and the result is stored in the destination effective address. The operands must be stored in the data registers or in memory. If the operands are stored in memory, they must be referenced in ARI with Predecrement Mode.

SWAP:Swap Register Halves
Operation:Register bits 16-32 <=> Register bits 0-15
Syntax:SUBX Dn
Attributes:Size = Word
Exchanges the upper and lower words of a data register.

TAS:Test and Set
Operation:Destination tested =>CCR, bit 7 of operand set
Syntax:TAS <ea>
Attributes:Size = Byte
The instruction will test the destination operand and set the Z and N bits appropriately, then set bit 7 of the destination location.
Addressing Mode
S/D
Addressing Mode
S/D
Dn
D
d(An,Xn)
D
An
.
Abs. Sh
D
(An)
D
Abs. Long
D
(An)+
D
Imm.
.
-(An)
D
d(PC)
.
d(An)
D
d(PC,Xn)
.

TST:Test Operand
Operation:Destination tested =>CCR
Syntax:TST <ea>
Attributes:Size = Byte
Compares the destination operand with 0 and sets the CCR accordingly.
Addressing Mode
S/D
Addressing Mode
S/D
Dn
D
d(An,Xn)
D
An
.
Abs. Sh
D
(An)
D
Abs. Long
D
(An)+
D
Imm.
.
-(An)
D
d(PC)
D
d(An)
D
d(PC,Xn)
D

Send comments to: sjkuyath@uncc.edu
Copyright Stephen J Kuyath, UNCC
last modified: January 3, 2007